View HCPL-0708_2669801.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description available in so-8 package, the HCPL-0708 optocoupler utilizes the latest cmos ic technology to achieve outstanding performance with very low power consumption. basic building blocks of the hcpl- agilent HCPL-0708 high speed cmos optocoupler data sheet features +5 v cmos compatibility 15 ns typical pulse width distortion 30 ns max. pulse width distortion 40 ns max. propagation delay skew high speed: 15 mbd 60 ns max. propagation delay 10 kv/ s minimum common mode rejection ?0 to 100 c temperature range safety and regulatory approvals pending ul recognized 3750 v rms for 1 min. per ul 1577 for HCPL-0708 csa component acceptance notice #5 iec/en/din en 60747-5-2 approved for HCPL-0708 option 060 applications scan drive in pdp digital field bus isolation: devicenet, sds, profibus multiplexed data transmission computer peripheral interface microprocessor system interface dc/dc converter functional diagram 0708 are a high speed led and a cmos detector ic. the detector incorporates an integrated photodiode, a high-speed trans- impedance amplifier, and a voltage comparator with an output driver. *a 0.1 f bypass capacitor must be connected between pins 5 and 8. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. 8 7 6 1 3 5 2 4 nc anode cathode nc v dd v o gnd led off on truth table nc v o , output h l
2 ordering information package outline drawing HCPL-0708 (small outline so-8 package) specify part number followed by option number (if desired) example HCPL-0708#xxxx 060 = iec/en/din en 60747-5-2 option. 500 = tape and reel packaging option. xxxe = lead free option. remarks: the notation ??is used for existing products, while (new) products launched since 15th july 2001 and lead free option will use ? xxxv yww 8765 4 3 2 1 5.994 ?0.203 (0.236 ?0.008) 3.937 ?0.127 (0.155 ?0.005) 0.406 ?0.076 (0.016 ?0.003) 1.270 (0.050) bsc 5.080 ?0.127 (0.200 ?0.005) 3.175 ?0.127 (0.125 ?0.005) 1.524 (0.060) 45?x 0.432 (0.017) 0.228 ?0.025 (0.009 ?0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 ?0.254 (0.205 ?0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 ?0.102 (0.008 ?0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
3 solder reflow thermal profile regulatory information the HCPL-0708 has been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca88324. 0 time (seconds) temperature ( c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 c 140 c 150 c peak temp. 245 c peak temp. 240 c peak temp. 230 c soldering time 200 c preheating time 150 c, 90 + 30 sec. 2.5 c 0.5 c/sec. 3 c + 1 c/ 0.5 c tight typical loose room temperature preheating rate 3 c + 1 c/ 0.5 c/sec. reflow heating rate 2.5 c 0.5 c/sec. recommended pb-free ir profile iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01 (option 060 only) 217 c ramp-down 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c
4 insulation and safety related specifications parameter symbol value units conditions minimum external air l(i01) 4.9 mm measured from input terminals to output gap (clearance) terminals, shortest distance through air. minimum external l(i02) 4.8 mm measured from input terminals to output tracking (creepage) terminals, shortest distance path along body. minimum internal plastic 0.08 mm insulation thickness between emitter and gap (internal clearance) detector; also known as distance through insulation. tracking resistance cti 175 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia material group (din vde 0110, 1/89, table 1) all agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
5 iec/en/din en 60747-5-2 insulation related characteristics (option 060) description symbol HCPL-0708 option 060 units installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i-iv for rated mains voltage 300 v rms i-iii for rated mains voltage 450 v rms climatic classification 55/85/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 560 v peak input to output test voltage, method b? v pr 1050 v peak v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc input to output test voltage, method a? v pr 840 v peak v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage? v iotm 4000 v peak (transient overvoltage, t ini = 10 sec) safety limiting values (maximum values allowed in the event of a failure, also see thermal derating curve, figure 11.) case temperature t s 150 c input current i s,input 150 ma output power p s,output 600 mw insulation resistance at t s , v 10 = 500 v r io 10 9 ? ?refer to the front of the optocoupler section of the isolation and control component designer s catalog , under product safety regulations section iec/en/din en 60747-5-2, for a detailed description. note: these optocouplers are suitable for safe electrical isolation only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. note: the surface mount classification is class a in accordance with cecc 00802. recommended operating conditions parameter symbol min. max. units figure ambient operating temperature t a 40 +100 c supply voltages v dd 4.5 5.5 v input current (on) i f 10 16 ma 1, 2 absolute maximum ratings parameter symbol min. max. units figure storage temperature t s 55 125 c ambient operating temperature [1] t a 40 +100 c supply voltages v dd 0 6 volts output voltage v o 0.5 v dd2 +0.5 volts average output current i o 2ma average forward input current i f 20 ma lead solder temperature 260 c for 10 sec., 1.6 mm below seating plane solder reflow temperature profile see solder reflow temperature profile section
6 electrical specifications over recommended temperature (t a = 40 c to +100 c) and 4.5 v v dd 5.5 v. all typical specifications are at t a = 25 c, v dd = +5 v. parameter symbol min. typ. max. units test conditions fig. notes input forward voltage v f 1.3 1.5 1.8 v i f = 12 ma 1 input reverse bv r 5vi r = 10 a breakdown voltage logic high output v oh 4.0 4.8 v i f = 0, i o = 20 a voltage logic low output v ol 0.01 0.1 v i f = 12 ma, i o = 20 a voltage input threshold current i th 8.2 ma i ol = 20 a2 logic low output i ddl 6.0 14.0 ma i f = 12 ma 4 supply current logic high output i ddh 4.5 11.0 ma i f = 0 3 supply current switching specifications over recommended temperature (t a = 40 c to +100 c) and 4.5 v v dd 5.5 v. all typical specifications are at t a = 25 c, v dd = +5 v. parameter symbol min. typ. max. units test conditions fig. notes propagation delay time t phl 20 35 60 ns i f = 12 ma, c l = 15 pf 5 1 to logic low output cmos signal levels propagation delay time t plh 13 21 60 ns i f = 12 ma, c l = 15 pf 5 1 to logic high output cmos signal levels pulse width pw 100 ns pulse width distortion |pwd| 0 14 30 ns i f = 12 ma, c l = 15 pf 2 2 cmos signal levels propagation delay skew t psk 40 ns i f = 12 ma, c l = 15 pf 3 3 cmos signal levels output rise time t r 20 ns i f = 12 ma, c l = 15 pf (10 - 90%) cmos signal levels output fall time t f 25 ns i f = 12 ma, c l = 15 pf (90 - 10%) cmos signal levels common mode |cm h | 10 15 kv/ sv cm = 1000 v, t a = 25 c, 4 4 transient immunity at i f = 0 ma logic high output common mode |cm l | 10 15 kv/ sv cm = 1000 v, t a = 25 c, 5 5 transient immunity at i f = 12 ma logic low output
7 package characteristics all typicals at t a = 25 c. parameter symbol min. typ. max. units test conditions input-output insulation i i-o 1 a 45% rh, t = 5 s v i-o = 3 kv dc, t a = 25 c input-output momentary v iso 3750 vrms rh 50%, t = 1 min., withstand voltage t a = 25 c input-output resistance r i-o 10 12 ? v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 25 c notes: 1. t phl propagation delay is measured from the 50% level on the risiing edge of the input pulse to the 2.5 v level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 v level of the rising edge of the v o signal. 2. pwd is defined as |t phl - t plh |. 3. t psk is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 4. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
8 figure 1. typical input diode forward characteristic. figure 2. typical input threshold current vs. temperature. figure 3. typical logic high o/p supply current vs. temperature. figure 4. typical logic low o/p supply current vs. temperature. figure 5. typical switching speed vs. pulse input current. i th input threshold current ma -40 2 t a temperature c 100 7 3 85 025 8 6 4 5 v dd = 5.0 v i ol = 20 a i ddh logic high output supply current ma -40 2.0 t a temperature c 100 5.5 3.0 85 025 6.0 4.5 3.5 4.0 v dd = 5.0 v 2.5 5.0 i ddl logic low output supply current ma -40 4.0 t a temperature c 100 7.5 5.0 85 025 8.0 6.5 5.5 6.0 v dd = 5.0 v 4.5 7.0 tp propagation delay ns 5 0 i f pulse input current ma 14 45 10 11 79 50 30 20 25 5 40 6 8 10 12 13 15 35 v dd = 5.0 v t a = 25 c t phl t plh pwd v f forward voltage v 100 10 0.1 0.01 1.1 1.2 1.3 1.4 i f forward current ma 1.6 1.5 1.0 0.001 1000 i f v f + t = 25 c a
9 application information bypassing and pc board layout the HCPL-0708 optocoupler is extremely easy to use. no external interface circuitry is required because the HCPL-0708 uses high-speed cmos ic technology allowing cmos logic to be connected directly to the inputs and outputs. as shown in figure 6, the only external component required for proper operation is the bypass capacitor. capacitor values should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 7 illustrates the recommended printed circuit board layout for the hpcl-0708. figure 6. recommended printed circuit board layout. figure 7. recommended printed circuit board layout. propagation delay, pulse-width distortion and propagation delay skew propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. the propaga- tion delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. see figure 8. figure 8. input t plh t phl output v i v o 10% 90% 90% 10% v oh v ol 0 v 50% 5 v cmos 2.5 v cmos 7 5 6 8 2 3 4 1 gnd c nc v dd v o v i xxx yww c1, c2 = 0.01 f to 0.1 f v dd c2 xxx yww v o gnd v i c1, c2 = 0.01 f to 0.1 f
figure 9. propagation delay skew waveform. figure 10. parallel data transmission example. propagation delay skew repre- sents the uncertainty of where an edge might be after being sent through an optocoupler. figure 10 shows that there will be uncertainty in both the data and clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the HCPL-0708 optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. pulse-width distortion (pwd) is the difference between t phl and t plh and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20 - 30% of the minimum pulse width is tolerable; the exact figure depends on the particular application. propagation delay skew, t psk , is an important parameter to con- sider in parallel data applications where synchronization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. if this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. propagation delay skew is defined as the difference between the minimum and maximum propa- gation delays, either t plh or t phl , for any given group of optocoup- lers which are operating under the same conditions (i.e., the same drive current, supply volt- age, output load, and operating temperature). as illustrated in figure 9, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the difference between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 10 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. the figure shows data and clock signals at the inputs and outputs of the optocouplers. in this case the data is assumed to be clocked off of the rising edge of the clock. 50% 50% t psk v i v o v i v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t psk t psk 10
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152 (domestic/interna- tional), or 0120-61-1280 (domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2005 agilent technologies, inc. obsoletes 5989-0295en february 28, 2005 5989-2132en

▲Up To Search▲

Price & Availability of HCPL-0708

	To Download HCPL-0708 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .